Principal Engineer – STA

🕒 July 27

🇮🇳 India – Remote

⏰ Full Time

🔴 Lead

🧑‍💻 Full-stack Engineer

👻 Ghost score 37%

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TYLsemi

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2026

🔧 Hardware

🤖 Artificial Intelligence

🤝 B2B

Hardware • Artificial Intelligence • B2B

TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functions—XPUs, switches, connectivity, power, and system scaling—and it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.

📋 Description

• Lead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs. • Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios. • Define timing constraints, validate SDCs, and ensure robust timing methodology execution. • Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence. • Analyze and resolve complex timing violations and critical path bottlenecks. • Support ECO implementation and signoff verification for advanced node tape-outs. • Develop and improve automation flows, scripts, timing dashboards, and methodology enhancements. • Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

🎯 Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. • 12+ years of experience in STA and timing signoff for ASIC/SOC programs. • Strong expertise in setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques. • Hands-on experience with Synopsys PrimeTime, Tempus, StarRC, and related signoff tools. • Strong understanding of SI, OCV/AOCV/POCV, CDC, low-power timing methodologies, and advanced node effects. • Experience with advanced technology nodes such as 7nm, 5nm, or below. • Strong scripting skills in Tcl, Python, Perl, or Shell scripting. • Excellent technical leadership, debugging, communication, and stakeholder management skills. • Good to Have: Experience with package-aware timing analysis and chiplet architectures. Exposure to AI/ML-driven timing optimization methodologies. Familiarity with automotive or high-reliability SOC design standards.

🏖️ Benefits

• No Politics, No Bureaucracy • Remote-Friendly, Global Team • Move Fast, Ship Real Products