Synthesis or Formal Verification Developer

Job not on LinkedIn

🔥 13 hours ago

🇦🇹 Austria – Remote

💵 €6k / month

⏳ Contract/Temporary

🟡 Mid-level

🟠 Senior

🖥 Software Engineer

👻 Ghost score 6%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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YosysHQ

WebsiteLinkedInAll Job Openings

1 - 10 employees

🔧 Hardware

Hardware

YosysHQ is the team behind Yosys and related Open Source EDA (Electronic Design Automation) projects, offering commercial products and services. They focus on providing solutions that enhance the design process in electronics engineering and support the development of tools for hardware design.

📋 Description

• Contribute to YosysHQ’s synthesis or formal verification areas • Develop and maintain tools using C++, Rust, and Python • Work on implementation of hardware model checking and formal methods, or RTL/ASIC synthesis workflows • Build software for engineering or science applications, implement algorithms from scientific literature, or work on compiler-related projects • Become familiar with and contribute to a large pre-existing open-source project • Take responsibility for assigned tasks and address challenges independently • Contribute to Yosys and the open-source EDA ecosystem • Potentially interact with or contribute to YosysHQ’s open-source tools

🎯 Requirements

• Comfortable with C++ or Rust for formal verification; willingness to learn the other languages, including Python • Familiarity with implementation of hardware model checking is ideal • Alternatively, background in verification or formal methods such as SAT/SMT solving, automated/interactive theorem proving, programming language theory, or automata theory • Some contact with RTL hardware design for formal verification • Comfortable with C++ for synthesis • Some experience with RTL hardware design, ideally for ASIC • Experience building software for engineering or science applications, implementing algorithms from scientific literature, or working on a compiler may transfer to the role • Experience becoming familiar with a large pre-existing project • Ability to take responsibility for assigned tasks and work independently without extensive supervision • Must not live in a country subject to sanctions or export restrictions, or be banned from performing work for the US government • CV and brief cover letter required for application

🏖️ Benefits

• Flexible remote work • Flexible working hours • Part-time option (1–5 days per week) • Flat pay hierarchy with the same rate for everyone • Ability to work from wherever you are • Team meetings usually between 3pm and 6pm Vienna time (CET/CEST), otherwise choose working hours