ASIC Core DFT Technical Lead – Scan, ATPG, BIST

🔥 13 minutes ago

🏄 California, Massachusetts, +2 more states – Remote

🏄 California – Remote 🍂 Massachusetts – Remote 🤠 Texas – Remote ☕ Washington – Remote

💵 $186.9k - $267.7k / year

⏰ Full Time

🟠 Senior

🧑‍💻 Full-stack Engineer

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Cisco

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1984

🔧 Hardware

🔐 Security

🏢 Enterprise

Hardware • Security • Enterprise

Cisco is a multinational technology company that provides networking hardware, software, and services to enterprises, service providers, and governments. It builds routers, switches, optical transceivers, programmable silicon, and edge computing platforms, and offers security, collaboration (Webex), observability, and AI-enabled software and support services to help organizations design, operate, and secure large-scale networks and data centers. Cisco also delivers professional services, training, and cloud-managed solutions to support digital transformation and AI-ready infrastructure.

📋 Description

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs • Responsible for development of innovative DFT IP in collaboration with the multi-functional teams • Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows • Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die

🎯 Requirements

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience • Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug • Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime • Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design • Prior experience with Tcl and Python/Perl • Verilog design experience – developing custom DFT logic & IP integration

🏖️ Benefits

• medical, dental and vision insurance • a 401(k) plan with a Cisco matching contribution • paid parental leave • short and long-term disability coverage • basic life insurance • 10 paid holidays per full calendar year • 1 floating holiday for non-exempt employees • 1 paid day off for employee’s birthday • paid year-end holiday shutdown • 4 paid days off for personal wellness • 16 days of paid vacation time per full calendar year for non-exempt employees • flexible vacation time off program for exempt employees • 80 hours of sick time off provided on hire date and each January 1st thereafter • optional 10 paid days per full calendar year to volunteer