Lead Signal & Power Integrity Hardware ASIC Simulation Engineer

🔥 24 minutes ago

🏄 California – Remote

🏄 California – Remote

💵 $183.8k - $263.6k / year

⏰ Full Time

🟠 Senior

🔧 Hardware Engineer

Apply Now

Find Similar Remote Jobs

Set Up Email Alert For New Jobs

📊 Check your resume score for this job

Improve your chances of getting an interview by checking your resume score before you apply.

Upload Resume

Cisco

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1984

🔧 Hardware

🔐 Security

Hardware • Security

Cisco is a multinational technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-level technology services and products. Cisco builds networking, security, observability, collaboration, and AI-optimized infrastructure for enterprises, service providers, data centers, and edge environments—offering products such as routers, switches, firewalls, programmable silicon (Silicon One), AI networking solutions, hybrid mesh firewall, smart switches, Cisco Cloud Control, Cisco IQ, and services for digital resilience and infrastructure modernization. The company targets large enterprises, hyperscalers, service providers, and governments, and is a market leader in networking and security with broad adoption across Fortune 500 companies.

📋 Description

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products. • Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB. • Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. • Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules. • Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments. • Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs. • Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met. • Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

🎯 Requirements

• Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience. • High-Speed Design & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction. • SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS. • Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation. • Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.

🏖️ Benefits

• medical, dental and vision insurance • 401(k) plan with a Cisco matching contribution • paid parental leave • short and long-term disability coverage • basic life insurance • 10 paid holidays per full calendar year • 1 floating holiday for non-exempt employees • 1 paid day off for employee’s birthday • paid year-end holiday shutdown • 4 paid days off for personal wellness determined by Cisco • 16 days of paid vacation time per full calendar year for non-exempt employees • flexible vacation time off program for exempt employees • 80 hours of sick time off provided on hire date and each January 1st thereafter • up to 80 hours of unused sick time carried forward from one calendar year to the next • optional 10 paid days per full calendar year to volunteer • annual bonuses for non-sales roles