Staff Design Engineer, IC Layout

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🔥 2 minutes ago

🇺🇸 United States – Remote

💵 $136k - $204k / year

⏰ Full Time

🔴 Lead

🧑‍🔧 Mechanical Engineer

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University of Washington, Department of Electrical & Computer Engineering

WebsiteLinkedInAll Job Openings

501 - 1000 employees

Founded 1905

📚 Education

🔬 Science

Education • Engineering • Science

University of Washington, Department of Electrical & Computer Engineering is an academic department that focuses on advancing education and research in electrical and computer engineering. It provides a range of undergraduate and graduate programs, emphasizes innovation in engineering, and conducts cutting-edge research in various fields such as microelectronics, robotics, and quantum technology. The department fosters a diverse and inclusive community and offers numerous opportunities for students to engage in hands-on learning, research, and collaboration with industry leaders.

📋 Description

• Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for high-performance RF and ultra-low-power, compact RFID • Work with analog and digital design teams on floor planning, pin placement, power supply strategy, and signal distribution between blocks • Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling • Participate in schedule meetings coordinating layout and floorplan activities • Deliver tape-outs for RFID products, test chips, reader ICs, and design-of-experiments work • Collaborate internationally with the analog RFID endpoint IC development team and Reader IC team

🎯 Requirements

• Bachelor’s degree in computer or electrical engineering • 8+ years of experience • Experience in custom analog, RF, and mixed-signal layout • Ability to collaborate with layout engineers on top-level IC floorplans and partner with circuit designers to resolve complex problems • Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm • Knowledge of analog layout challenges and layout-dependent effects, including noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring • Knowledge of mitigation techniques including guard rings, DNW, PN junctions, parasitic management, signal integrity, EMIR, and ESD • Proficiency with Cadence Virtuoso layout editor • Proficiency with Cadence/Siemens layout verification tools, including PVS and Siemens Calibre DRC/LVS • Ability to interpret and correct ERC, DRC, and LVS error reports • Excellent communication and collaboration skills • Strong technical project management skills • Must satisfy applicable U.S. export control requirements; additional national identity documentation may be required to determine export authorization

🏖️ Benefits

• Merit increases for eligible roles • Annual bonus for eligible roles • Stock for eligible roles • Sales incentives for eligible roles, depending on plan and role • Healthcare benefits for US-based employees • 401(k) plan and company match • Support for remote work • Open paid-time-off policy • Work/life balance support • Weekly Q&A sessions with the executive team • Competitive benefits • Reasonable accommodation for individuals with disabilities

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