PMTS, PEX Engineer – Quantum

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🔥 0 minutes ago

🌐 United States, Malta – Remote

🇺🇸 United States – Remote 🇲🇹 Malta – Remote

🗽 New York, Massachusetts – Remote

🗽 New York – Remote 🍂 Massachusetts – Remote

💵 $143k - $247k / year

⏰ Full Time

🟡 Mid-level

🟠 Senior

👷🏻‍♀️ Engineer

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This company has sponsored H1B visas in the past.

👻 Ghost score 2%

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GlobalFoundries

WebsiteLinkedInAll Job Openings

10,000+ employees

🏭 Manufacturing

🔧 Hardware

Manufacturing • Hardware

GlobalFoundries is one of the world’s leading semiconductor manufacturers. GF is redefining innovation and semiconductor manufacturing by developing and delivering feature-rich process technology solutions that provide leadership performance in pervasive high growth markets. GF offers a unique mix of design, development, and fabrication services. With a talented and diverse workforce and an at-scale manufacturing footprint spanning the U. S. , Europe and Asia, GF is a trusted technology source to its worldwide customers.

📋 Description

• Develop, code, qualify, and maintain DRC, LVS, and PEX rule decks and associated PDK components • Translate process integration requirements, design rules, device definitions, and electrical models into physical verification and extraction solutions • Develop regression and test methodologies to validate rule-deck correctness, coverage, performance, scalability, and compatibility • Analyze and debug complex DRC, LVS, and PEX issues, identify root causes, and resolve discrepancies with cross-functional teams • Partner with process technology, design rule, compact modeling, reliability, circuit design, layout, and EDA teams • Develop automation and AI/ML-assisted methodologies for rule generation, test generation, coverage assessment, error classification, anomaly detection, debugging, and continuous PDK verification • Optimize physical verification and extraction flows for accuracy, runtime, memory usage, scalability, usability, and production deployment • Drive PDK quality and release readiness through qualification, regression testing, documentation, change management, and continuous improvement • Perform activities safely and support Environmental, Health, Safety & Security programs • Work and collaborate on other projects and assignments as needed

🎯 Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field • Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level • Experience with DRC and/or LVS rule development, coding, debug, or qualification • Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance • Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions • Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies • Experience with Python, Tcl, Perl, shell scripting, or equivalent for engineering automation, regression testing, and data analysis • Ability to troubleshoot complex technical problems, perform structured root-cause analysis, and translate findings into robust engineering solutions • Willingness to travel up to 10% • Written and verbal fluency in English • Preferred: Master's degree or PhD in a related technical field • Preferred: Experience releasing production PDK DRC, LVS, and/or PEX rule decks • Preferred: Experience with Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or equivalent • Preferred: Experience with PEX technology-file development, RC extraction, process-corner modeling, and silicon/model correlation • Preferred: Experience with automated regression environments, rule coverage metrics, test structures, or PDK qualification methodologies • Preferred: Experience applying AI/ML, generative AI, or data-driven techniques to semiconductor design enablement • Preferred: Understanding of interactions among process integration, design rules, OPC/lithography, device modeling, reliability, extraction, and circuit design • Preferred: Experience collaborating with EDA vendors and design teams • Preferred: Strong written and verbal communication skills • Preferred: Strong planning and organizational skills

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