Compiler Engineer – Algorithmic Workloads

Job not on LinkedIn

🕒 March 19

🏄 California – Remote

🏄 California – Remote

⏰ Full Time

🟡 Mid-level

🟠 Senior

👷🏻‍♀️ Engineer

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Mythic

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2012

🤖 Artificial Intelligence

🔧 Hardware

💰 $70M Series C on 2021-05

Artificial Intelligence • Hardware • Robotics

Mythic is the leading high-performance analog computing company that focuses on delivering cost-efficient and energy-efficient edge AI computing power across various sectors including robotics, defense, and consumer devices. The company's innovative compute-in-memory technology solves the limitations of traditional digital computing by storing AI parameters directly in the processor, significantly enhancing AI inference applications. Mythic aims to empower industries with advancements in performance scalability and efficiency, providing a robust platform for the next generation of AI applications.

📋 Description

• Help push the boundaries of what can run on our accelerator. • Design compiler IRs and lowering strategies to support algorithmic workloads with irregular or dynamic control flow—loops, branches, and iterative methods—going beyond static neural networks. • Work side by side with hardware engineers to influence ISA and execution model co-design to unlock new algorithm classes on analog and digital subsystems. • Create a compiler that makes complex algorithms practical to deploy while staying seamless for developers.

🎯 Requirements

• 3+ years of professional experience in compilers or high-performance systems software • Proficiency in modern C++ (C++14/17/20) and Python • Familiarity with compiler IRs (e.g., MLIR, LLVM, or equivalent) and their use representing complex program structures • Solid foundation in program analysis and optimization techniques (e.g., SSA form, loop optimizations, vectorization)

🏖️ Benefits

• The opportunity to make algorithmic and control-flow-heavy workloads practical on novel accelerator hardware. • A role that bridges compiler design and hardware co-design, shaping both the IR and the accelerator architecture. • A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design. • Competitive compensation, equity, and benefits package.