Asics Engineer

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🔥 12 hours ago

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SAPSOL Technologies Inc. : Systems and Process Solutions for your Enterprise

WebsiteLinkedInAll Job Openings

201 - 500 employees

🏢 Enterprise

☁️ SaaS

🤖 Artificial Intelligence

Enterprise • SaaS • Artificial Intelligence

SAPSOL Technologies Inc. is a leader in innovative business transformation, expertly integrating ERP systems, AI, cloud computing, and DevOps to deliver cutting-edge solutions for businesses of all sizes. Specializing in S/4HANA implementation, system migration, and managed support services, SAPSOL ensures seamless integration and optimization of business processes. The company offers advanced business intelligence tools for actionable insights, enabling smarter decision-making and performance enhancement across key operational areas. SAPSOL excels in rapid go-to-market strategies, managing complex global rollouts with precision. Their expertise in process optimization, automation, change management, emerging technology, cloud, AI, and analytics transforms supply chains, financial reporting, and customer service to enhance efficiency and reduce costs. SAPSOL also provides a range of services including security, cloud, and big data analytics, supporting enterprises in staying agile and competitive. The SAPSOL Product Innovation Lab (SPIL) drives advancements like HireRig, an AI-driven recruitment platform. Based in North America, SAPSOL collaborates with startups and invests in disruptive ideas, leveraging partnerships with SAP, Oracle, IBM, and Microsoft technologies to shape the future of business transformation.

📋 Description

• Architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality • Act as a technical escalation point for advanced DFT and post-silicon debug issues • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity

🎯 Requirements

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT) • Strong hands-on experience in ASIC DFT with end-to-end ownership • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis • Experience with MBIST implementation and verification; SMS experience preferred • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation • Proven post-silicon debug and silicon bring-up experience • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges • Strong communication skills and the ability to work independently with minimal ramp-up