Front End Design Verification Engineer

🔥 0 minutes ago

🏄 California – Remote

🏄 California – Remote

💵 $100k - $500k / year

⏰ Full Time

🟡 Mid-level

🟠 Senior

💻 Frontend Engineer / Web Developer

👻 Ghost score 2%

What it means: the chance that no one is really hiring for this job.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Tenstorrent Inc.

WebsiteLinkedInAll Job Openings

51 - 200 employees

Founded 2016

🏭 Manufacturing

💼 Consulting

🤖 Artificial Intelligence

Manufacturing • Consulting • Artificial Intelligence

Tenstorrent is a cutting-edge technology company based in Santa Clara, CA, specializing in AI semiconductors and computing solutions. They have developed advanced products like the TT-QuietBox, a liquid-cooled workstation designed for AI model development, and the Tenstorrent Galaxy, a high-performance AI compute server. Recently, Tenstorrent secured over $693M in Series D funding to enhance its AI chip capabilities and challenge market leaders in the AI data center sector.

📋 Description

• Verify the fetch unit for next-generation high-performance RISC-V CPU cores • Develop verification strategies and sophisticated tests • Debug complex failures and ensure front-end correctness across workloads and corner cases • Collaborate closely with CPU architects, RTL designers, and other design verification engineers • Verify instruction fetch, prediction, decode, and dispatch logic • Verify speculative execution and corner cases involving branches, redirects, exceptions, and pipeline flushes • Translate architectural specifications and microarchitectural designs into RTL and comprehensive verification environments • Support processors designed for AI, HPC, and high-performance computing workloads

🎯 Requirements

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs • Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development • Solid understanding of CPU architecture, including pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution • Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools • Strong programming skills in C/C++ and/or Python • Ability to collaborate effectively across architecture, RTL, DV, and software teams • Eligibility to access U.S. export-controlled technology, including compliance with applicable export laws and possible citizenship/permanent residency or license requirements

🏖️ Benefits

• Highly competitive compensation package and benefits

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