DFT Engineer

Job not on LinkedIn

🔥 0 minutes ago

🏄 California – Remote

🏄 California – Remote

⏰ Full Time

🟠 Senior

🔴 Lead

👷🏻‍♀️ Engineer

👻 Ghost score 18%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Unconventional AI

WebsiteLinkedInAll Job Openings

11 - 50 employees

🤖 Artificial Intelligence

🔧 Hardware

⚡ Energy

Artificial Intelligence • Hardware • Energy

Unconventional AI is rethinking the foundations of a computer to optimize energy efficiency for AI. Founded by experts in AI systems, analog circuits, computing theory, and neuroscience, the company aims to bring biology-scale efficiency to artificial intelligence by redesigning computing architecture and hardware to reduce power consumption for AI workloads.

📋 Description

• Lead implementation of comprehensive test architectures using industry-standard CAD tools, including scan compression, MBIST, and JTAG/boundary scan logic • Drive bottom-up hierarchical DFT methodologies for large-scale SoC designs, including core-level test wrapping, pattern retargeting, and top-level test integration • Own DFT strategy and work with foundry interfaces to analyze defect densities and improve test-chip yield • Drive DFT methodologies for 2.5D/3D multi-stacked die packaging and ensure test coverage across die-to-die interfaces using standards such as IEEE 1838 • Facilitate integration and testability of custom analog mixed-signal blocks and develop test strategies for non-standard analog macros • Drive test coverage, test time, and yield targets while influencing micro-architecture for improved Power, Performance, and Area (PPA) • Own final DFT sign-off, including ATPG, test-vector validation, fault simulation, and timing closure during STA for all test modes • Contribute to design-flow development and automation and establish testability best practices for first-pass silicon success • Evaluate potential AI-tool partners that could improve chip-design efficiency

🎯 Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field • 10+ years of industry experience in digital DFT and test architecture • Track record of successful tapeouts on modern process nodes; 7nm, 5nm, or newer preferred • Deep expertise in scan compression, MBIST generation, fault modeling (stuck-at, transition, path delay), and ATPG • Deep understanding of physical design challenges in advanced nodes, including multi-patterning, finFET effects, and low-voltage operation, and their impact on test reliability • Expertise in Static Timing Analysis (STA) and timing closure for complex designs in shift and capture test modes • Expert-level mastery of standard EDA CAD tool suites for DFT implementation and vector generation • Strong scripting skills in Tcl, Python, or Perl for design-flow automation and data analysis • Excellent written and verbal communication skills • Experience managing deliverables from external vendors or design houses