Cerebras Systems
Artificial Intelligence • Hardware • Healthcare Insurance
Cerebras Systems is a pioneering company that focuses on developing advanced AI hardware, specifically the Cerebras Wafer Scale Engine, which delivers unparalleled performance in AI inference, outperforming traditional GPU setups. Their cutting-edge technology enables organizations like Mayo Clinic and AlphaSense to run state-of-the-art AI models with remarkable speed and efficiency. With flexible deployment options including cloud and on-premises solutions, Cerebras is transforming the landscape of AI capabilities for innovative teams across various industries.
SOC Physical Design Integration Lead
Job not on LinkedIn
October 7
Cerebras Systems
Artificial Intelligence • Hardware • Healthcare Insurance
Cerebras Systems is a pioneering company that focuses on developing advanced AI hardware, specifically the Cerebras Wafer Scale Engine, which delivers unparalleled performance in AI inference, outperforming traditional GPU setups. Their cutting-edge technology enables organizations like Mayo Clinic and AlphaSense to run state-of-the-art AI models with remarkable speed and efficiency. With flexible deployment options including cloud and on-premises solutions, Cerebras is transforming the landscape of AI capabilities for innovative teams across various industries.
📋 Description
• Join our close-knit physical design team where you'll excel in synthesizing, placing, routing and integrating high speed designs. • Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture.
🎯 Requirements
• 10+ years of physical design, integration & physical verification experience. • Strong knowledge of block level and full-chip physical verification methodology. • Experience with the complete physical design flow. • Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools • Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. • Expert with IR/EM analysis and resolution • Good understanding of full chip floor planning and integration. • Strong experience in full chip timing closure • Demonstrated ability to work with RTL teams to optimize for physical design • Ability to independently debug and resolve physical verification Issues • BS or MS in Electrical Engineering
🏖️ Benefits
• Health insurance • Retirement plans • Paid time off • Flexible work arrangements • Professional development
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