
10,000+ employees
Founded 1984
🔧 Hardware
🔐 Security
🏢 Enterprise
Hardware • Security • Enterprise
Cisco is a multinational technology company that provides networking hardware, software, and services to enterprises, service providers, and governments. It builds routers, switches, optical transceivers, programmable silicon, and edge computing platforms, and offers security, collaboration (Webex), observability, and AI-enabled software and support services to help organizations design, operate, and secure large-scale networks and data centers. Cisco also delivers professional services, training, and cloud-managed solutions to support digital transformation and AI-ready infrastructure.
🕒 May 23
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10,000+ employees
Founded 1984
🔧 Hardware
🔐 Security
🏢 Enterprise
Hardware • Security • Enterprise
Cisco is a multinational technology company that provides networking hardware, software, and services to enterprises, service providers, and governments. It builds routers, switches, optical transceivers, programmable silicon, and edge computing platforms, and offers security, collaboration (Webex), observability, and AI-enabled software and support services to help organizations design, operate, and secure large-scale networks and data centers. Cisco also delivers professional services, training, and cloud-managed solutions to support digital transformation and AI-ready infrastructure.
• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. • Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. • Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. • The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4-8 years of experience . • Knowledge of the latest innovative trends in DFT, test and silicon engineering. • Experience with Jtag protocols, Scan insertion and ATPG, BScan • Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets. • Experience working with Gate level simulation, debugging with VCS and other simulators. • Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 • Strong verbal skills and ability to thrive in a multifaceted environment • Scripting skills: Tcl, Python/Perl. • Test Static Timing Analysis • Post silicon validation using DFT patterns.
Apply Now🕒 May 22
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