PCIe ASIC Design Engineer

May 25

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Cornelis Networks

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Artificial Intelligence • Hardware • Enterprise

Cornelis Networks is a leading provider of intelligent, scalable, high-performance interconnects designed for AI applications. The company specializes in delivering end-to-end purpose-built high-performance fabrics to commercial, scientific, academic, and government organizations. Cornelis Networks’ solutions are aimed at enhancing performance, scalability, and efficiency across hyperscale, cloud AI, and on-premises AI/HPC environments. Their offerings are known for scalable architecture, high bandwidth solutions, and universal compatibility with accelerators and GPUs. Originating as an Intel spin-off, the company is positioned to challenge existing technologies like InfiniBand and Ethernet, providing advanced interconnects that power modern AI infrastructure.

51 - 200 employees

🤖 Artificial Intelligence

🔧 Hardware

🏢 Enterprise

💰 $29M Series B on 2022-11

📋 Description

• Lead the design and integration of PCIe controllers into next-generation SoCs • Own end-to-end integration of PCIe IP into complex ASIC designs • Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems • Drive performance optimization efforts across the PCIe stack • Contribute to system architecture and microarchitecture discussions • Lead silicon bring-up and validation of PCIe links in the lab • Debug functional and performance issues at RTL, gate-level, and silicon • Ensure compliance with PCIe specifications and participate in interoperability testing • Provide mentorship to junior engineers and help define PCIe subsystem development best practices • Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms

🎯 Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field • 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration • Proven experience in silicon bring-up and debug of high-speed interfaces • Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training • Hands-on experience with PCIe verification environments, performance tuning, and power-aware design • Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes) • Strong scripting (Python, Perl, TCL) and debugging skills • Strong verbal and written communication skills

🏖️ Benefits

• Competitive compensation package • Equity, cash, and incentives • Health and retirement benefits • Medical, dental, and vision coverage • Disability and life insurance • Dependent care flexible spending account • Accidental injury insurance • Pet insurance • Generous paid holidays • 401(k) with company match • Open Time Off (OTO) • Sick time, bonding leave, and pregnancy disability leave