Verification Engineer

Job not on LinkedIn

🔥 12 hours ago

🇵🇹 Portugal – Remote

⏰ Full Time

🟡 Mid-level

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 17%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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DOMVS iT

WebsiteLinkedInAll Job Openings

51 - 200 employees

Founded 2014

💼 Consulting

🏥 Healthcare

🏢 Enterprise

Consulting • Healthcare • Enterprise

DOMVS iT is a Brazilian technology services company with over a decade of experience that provides IT staffing (Squad as a Service), managed squads, consulting, outsourcing, application management, and cloud & data services. The firm offers digital experience and product design services (Product Discovery, PDaaS), cloud architecture, FinOps, migrations, data masking/virtualization, and enterprise application support (including SAP), serving business customers across multiple cities and countries.

📋 Description

• Develop and maintain constrained-random UVM testbenches for RTL blocks and full-chip verification • Create functional coverage models and coverage closure plans • Create and execute directed and randomized test scenarios, focusing on corner cases and protocol compliance • Debug simulation failures, identify root causes in the RTL, and collaborate with designers to implement fixes • Develop verification plans (VPlans) based on microarchitecture specifications and track sign-off metrics • Contribute to regression infrastructure, CI/CD pipelines, and script development for EDA tool flows • Participate in design reviews, specification reviews, and silicon bring-up activities • Verify the functional correctness of complex digital IP blocks and SoCs, collaborating with Design, Architecture, and Software teams

🎯 Requirements

• Bachelor's, Master's, or Ph.D. degree (B.Sc. / M.Sc. / Ph.D.) in Electrical Engineering, Computer Engineering, or a related field • 5+ years of hands-on experience in VLSI verification within an industrial environment • Strong proficiency in SystemVerilog and the UVM methodology, including environments, agents, sequences, and scoreboards • Strong proficiency in the Specman language and methodology • Experience with simulation tools such as VCS, Xcelium, and ModelSim/Questa • Solid understanding of digital design fundamentals, RTL coding, and microarchitecture concepts • Familiarity with assertion-based verification (SVA) and Coverage-Driven Verification • Scripting knowledge in Python, Perl, or Tcl for automation and flow development • Advanced English proficiency required

🏖️ Benefits

• 15 days of paid leave • Clude Saúde (online medical consultation platform) • Birthday day off + gift • AWS partnership • Language allowance • TotalPass • Support for specialization and certification programs (postgraduate/MBA programs and AWS certification) • Employee referral bonus • Méritos platform