Senior ASIC Physical Design Engineer

🕒 April 8

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K2 Space Corporation

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🚀 Aerospace

🔧 Hardware

🏛️ Government

Aerospace • Hardware • Government

K2 Space Corporation is a California-based aerospace manufacturer that designs and produces large, high-power satellite buses intended to deliver significantly more power, mass and payload volume at lower cost than traditional large satellites. The company emphasizes production-line style builds and commercial supply chains to shorten lead times and reduce per-unit cost, enabling multi-manifest launches and multi-orbit missions across LEO, MEO, GEO and cislunar space. K2 serves commercial, scientific and government/defense customers, and focuses on enabling missions that require high throughput, high-power payloads.

📋 Description

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. • Develop and maintain scripts and automation to improve flow efficiency and consistency. • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. • Assist in chip-level integration, ECOs, and tapeout preparation. • Contribute to methodology development, tool evaluation, and flow documentation. • Support your product through production and spaceflight.

🎯 Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field • 5–10 years of experience in ASIC physical design for complex SoCs • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent) • Strong understanding of timing analysis, power optimization, and physical verification flows • Experience with hierarchical or flat SoC design methodologies • Familiarity with FinFET technologies • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

🏖️ Benefits

• Comprehensive benefits package including paid time off • Medical/dental/vision coverage • Life insurance • Paid parental leave • Equity in the company