Senior Physical Design Engineer – LPU

🕒 March 12

🌵 Arizona, California, +3 more states – Remote

🌵 Arizona – Remote 🏄 California – Remote ⛰️ Colorado – Remote 🌲 North Carolina – Remote 🌲 Oregon – Remote

💵 $136k - $264.5k / year

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

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NVIDIA

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1993

🤖 Artificial Intelligence

🎮 Gaming

Artificial Intelligence • Gaming • Automotive

NVIDIA is a leading technology company specializing in accelerated computing and artificial intelligence. NVIDIA pioneers advancements in graphical processing units (GPUs), cloud computing, data centers, and virtual reality, with a focus on gaming, automotive, healthcare, and robotics industries. The company's innovations, such as NVIDIA Omniverse, transform traditional digital processes by enabling high-fidelity simulations and rendering tasks. Their applications span various industries, from autonomous vehicles using NVIDIA DRIVE to healthcare solutions with NVIDIA Clara, and AI-driven analytics and workflows.

📋 Description

• Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level • Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation • Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout • Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency

🎯 Requirements

• B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) • 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes • Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification • Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures • Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints • Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle • Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure • Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations • Expert-level command of industry-standard tool suites for end-to-end physical design flows • Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency • Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces a plus

🏖️ Benefits

• equity • health insurance