Senior Engineer, Layout Design

🕒 July 15

🇩🇪 Germany – Remote

⏰ Full Time

🟠 Senior

🧑‍💻 Full-stack Engineer

👻 Ghost score 14%

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SiTime

WebsiteLinkedInAll Job Openings

201 - 500 employees

Founded 2005

🏭 Manufacturing

💼 Consulting

📦 Logistics

Manufacturing • Consulting • Logistics

SiTime is a leader in precision timing solutions, specializing in MEMS (Micro-Electro-Mechanical Systems) technology that provides superior timing devices used in various industries, including automotive, aerospace, and communications. Their innovative products enhance system performance, reduce size, and deliver unmatched reliability in harsh environments, making them indispensable in advanced applications such as 5G, IoT, and automotive electronics.

📋 Description

• Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits • Perform schematic-driven layout and design constraints • Design die-area efficient layouts according to circuit designer requirements • Perform block or top-level layout designs • Perform floor-planning, power line planning, shielding, and device-matching layout • Verify layouts. Pass DRC, LVS, and ERC • Contribute to various chip-level routing and layout needs • Perform chip level integration, verifications, and tape-out • Support other projects as needed by management • Train junior layout engineers and offshore layout contractors • Contribute to developing common best practices and workflow across all sites • Contribute to build process and procedures to achieve high layout quality

🎯 Requirements

• BA/BS Degree in Layout Design or related field or equivalent experience • 10 years’ experience with layout design for analog and full-custom digital blocks • Proficient in using layout editing tools in the Cadence Virtuoso design environment • Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre • Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation • Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints • Experience in chip-level floor planning and analog block integration • Experience chip level integration, verifications, and tape-out • Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable • Attention to detail, organized, accurate and can produce efficient layout techniques

🏖️ Benefits

• quarterly bonus tied to the achievement of innovation goals • equity grants