Senior FPGA Developer, SystemVerilog

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🕒 January 29

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Terra Quantum AG

WebsiteLinkedInAll Job Openings

51 - 200 employees

Terra Quantum is a leading quantum technology company based in Germany and Switzerland. It provides "Quantum as a Service (QaaS)“ in three core areas, the first one being "Quantum Algorithms as a Service". Here, customers are provided access to an extensive library of algorithms, such as hybrid quantum optimization and hybrid quantum neural networks, which can be used for solving complex logistics problems or pattern recognition, among other things. Terra Quantum also develops new quantum algorithms for its customers or adapts existing algorithms to their specific needs. Secondly, through "Quantum Computing as a Service", Terra Quantum offers its customers access to its proprietary high-performance simulated quantum processing units (QPU), the quantum ecosystem’s physical QPUs, while also developing native QPUs. The third division is "Quantum Security as a Service," through which Terra Quantum offers its unique solutions for secure quantum and post-quantum communications worldwide.

📋 Description

• The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end-to-end RTL ownership on AMD/Xilinx (Artix-7, Kintex UltraScale): architect, implement, verify, and close timing on high-rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer. • The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring-up, and deliver reproducible, versioned bitstreams. • RTL architecture, interfaces, and rather high-speed datapaths • Owning SystemVerilog RTL architecture/implementation for Artix-7 and Kintex UltraScale (SystemVerilog, Vivado) • Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third-party MAC/PCS IP • Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low-level protocols — and bridging them to high-throughput interfaces (DDR/PCIe) • Defining clear AXI/AXI-Stream boundaries and register maps for SW/FW integration • Constraints, timing closure, and floorplanning • Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners • Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin • Verification and CI • Establishing a professional verification environment with ModelSim/Questa; developing self-checking testbenches and regression suites; integrating Python/cocotb co-simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as appropriate) • Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW in-the-loop smoke tests • Bring-up, debug, and releases • Board bring-up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring-up • Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts • Cross-team collaboration and mentoring • Driving system integration with SW/FW: register/driver contracts, throughput/latency budgets, HIL • Mentoring a junior engineer; codifying style guides, reviews, and design documentation

🎯 Requirements

• 5+ years production FPGA on AMD/Xilinx; expert SystemVerilog RTL • Demonstrated mentoring of junior engineers • Strong constraints/timing (XDC), CDC/reset, and practical floorplanning; consistent timing closure • Hands-on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third-party MAC/PCS IP • Strong verification background; experience with self-checking testbenches and regression testing, proficiency with ModelSim/Questa. Knowledge of OSVVM/UVM is a plus • CI for HDL: scripted sim/synth/impl (Tcl/Make/Python), lint, artifact/version management; board bring-up and ILA-based debug • System integration with SW/FW: register maps, driver contracts, HIL • Proficiency in written and spoken English • Ability to be on-site in Munich or Potsdam offices to work with hardware, when required

🏖️ Benefits

• An opportunity to work with some of the brightest minds in the pioneering field of Quantum Technologies as well as an experienced and progressive Leadership team • Gain knowledge of some of the most cutting-edge technology developments in science & engineering • A chance to be part of one of Europe’s leading technology firms of the upcoming decades • Welcoming, friendly, and professional colleagues • A personal development plan with clear goals for advancement • A competitive salary • Flexible working arrangements • A diverse and supportive atmosphere, where innovation and initiative are encouraged