DFT Architect

🕒 July 27

🇮🇳 India – Remote

⏰ Full Time

🟠 Senior

🔴 Lead

🏛️ Architect

👻 Ghost score 37%

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TYLsemi

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2026

🔧 Hardware

🤖 Artificial Intelligence

🤝 B2B

Hardware • Artificial Intelligence • B2B

TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functions—XPUs, switches, connectivity, power, and system scaling—and it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.

📋 Description

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs • Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies • Drive DFT planning and integration aligned with power, timing, area, and test coverage goals • Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff • Analyze and resolve DFT-related timing, routing, and testability challenges • Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization • Develop and enhance DFT automation flows, methodologies, and reusable infrastructure • Mentor junior engineers and provide technical leadership across projects

🎯 Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field • 10+ years of experience in ASIC/SOC DFT implementation and architecture • Strong expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies • Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent • Strong understanding of RTL design, timing, physical design constraints, and silicon debug • Experience with advanced technology nodes and large SOC integration • Strong scripting and automation skills using Tcl, Python, Perl, or Shell • Excellent leadership, problem-solving, and cross-functional collaboration skills

🏖️ Benefits

• Remote-Friendly, Global Team • Ownership mindset • Bias for action • Deep technical expertise • Low ego, high standards