Physical Design

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Weekday (YC W21)

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2021

💼 Consulting

👥 HR Tech

☁️ SaaS

Consulting • HR Tech • SaaS

Weekday is a modern recruitment platform that combines AI technologies with a vast database of potential candidates, aiming to streamline the hiring process for companies in India. They offer various services, including a proactive outreach approach that helps employers connect with top talent, as well as tools for candidates to easily apply for jobs. Weekday's emphasis on candidate engagement through multiple channels, including email, WhatsApp, and phone calls, sets it apart in the competitive landscape of recruitment agencies.

📋 Description

• Execute the complete Physical Design flow from Netlist to GDSII • Perform floorplanning, power planning, placement, clock tree synthesis, routing, and physical verification • Drive timing closure while meeting performance, power, and area targets • Perform congestion analysis and optimize placement and routing • Analyze and fix setup/hold timing violations across all design corners and modes • Perform physical signoff including DRC, LVS, IR Drop, EM, and antenna checks • Collaborate with RTL, DFT, STA, and Packaging teams to achieve successful tape-out • Debug and resolve implementation issues while ensuring design quality • Support ECO implementation and timing closure activities • Ensure successful tape-out on advanced technology nodes

🎯 Requirements

• 6+ years of hands-on experience in ASIC/SoC Physical Design • Strong experience in the complete RTL-to-GDSII implementation flow • Expertise in floorplanning, power planning, placement and optimization, CTS, routing, physical verification, and ECO implementation • Strong timing closure experience with setup and hold optimization • Hands-on experience with Cadence Innovus • Experience using Synopsys ICC2 is an added advantage • Strong knowledge of Static Timing Analysis (STA) concepts • Experience with IR Drop, EM Analysis, Crosstalk, Noise, and Signal Integrity • Hands-on experience with Calibre for DRC/LVS signoff • Experience with advanced technology nodes including 2nm, 3nm, 5nm, 7nm, 12nm, 16nm, and FinFET • Good understanding of low-power implementation techniques using UPF/CPF • Experience in block-level or chip-level tape-out • Strong debugging and problem-solving skills • Experience with Fusion Compiler implementation flow is good to have • Hands-on experience with Synopsys PrimeTime and PrimeTime-SI is good to have • Experience using RedHawk or Voltus for Power Integrity analysis is good to have • Knowledge of Formality and logical equivalence checking is good to have • Experience with hierarchical SoC implementation is good to have • Scripting skills in TCL, Python, or Perl are good to have • Exposure to multi-voltage and multi-power domain designs is good to have • Experience with CPU, GPU, AI/ML, Networking, Mobile, Automotive, or HPC SoCs is good to have • Familiarity with advanced packaging technologies such as 2.5D/3D ICs is good to have • Prior customer-facing or offshore/on-site collaboration experience is good to have • Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field is listed as preferred, not required • Ability to work independently and collaboratively in a fast-paced semiconductor development environment