Lead Analog Layout Engineer

🕒 3 days ago

🇨🇦 Canada – Remote

💵 C$141.7k - C$226k / year

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

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Ciena

WebsiteLinkedInAll Job Openings

5001 - 10000 employees

Founded 1985

📡 Telecommunications

🔧 Hardware

💰 Series C on 1995-12

Telecommunications • Hardware • Networking

Ciena is a global leader in optical and routing systems, services, and automation software. We build the world’s most adaptive networks to address ever-increasing digital demands for richer, more connected experiences for all users. For three-plus decades, we’ve brought our innate sense of humanity to our relentless pursuit of innovation.

📋 Description

• Own assigned layout projects from feasibility and floorplanning through implementation, physical verification, integration, and tapeout readiness • Define project scope, implementation plans, effort estimates, milestones, and review checkpoints • Coordinate contributors, track dependencies, and resolve implementation bottlenecks • Lead layout reviews and quality checks with layout teams and circuit designers • Establish implementation constraints and evaluate performance, area, device matching, parasitics, isolation, and reliability tradeoffs • Develop layout strategies for performance-critical circuits and high-speed signal paths • Review extracted parasitics and implement targeted improvements • Drive physical-verification and reliability closure, including DRC, LVS, ERC, antenna, BUMP, EM/IR, and PERC checks • Mentor junior engineers through hands-on problem-solving and design feedback • Partner with CAD and AI/ML engineers on environment setup, tool evaluation, automation, reusable layout structures, RFIC and analog layout generation, PCell development, and design space exploration • Communicate progress, risks, and corrective actions against milestones

🎯 Requirements

• Bachelor's degree or higher in Electrical Engineering, or a related field • 5+ years of custom analog or mixed-signal IC layout experience • Ownership of complex layouts through successful tapeouts • Independent technical decision-making and project delivery experience • Experience guiding layout contributors and hands-on implementation • Experience with ADCs, DACs, SerDes, PLLs, high-speed amplifiers, or precision analog circuits • Proficiency with Cadence Virtuoso and Siemens Calibre, or comparable custom-layout and physical-verification tools • Knowledge of device matching, parasitic resistance and capacitance, coupling, high-frequency routing, shielding, ESD-aware layout, electromigration, and IR drop • Knowledge of deep-submicron CMOS processes, foundry design rules, device isolation, and layout-dependent effects • Practical experience with FinFET layout and advanced-node implementation • Experience in high-speed SerDes or data converters • Experience with Ansys Totem or comparable EM/IR tools and PERC-based ESD and reliability debugging • Deep knowledge of noise isolation and shielding • PCell development and layout automation skills • Experience using AI-assisted coding tools for layout-flow scripts, automation, and engineering utilities

🏖️ Benefits

• Development opportunities • Flexible work arrangements • Medical, dental, and vision plans • DCPP (Canada) with company matching • Employee Stock Purchase Program (ESPP) • Employee Assistance Program (EAP) • Company-paid holidays • Paid sick leave • Vacation time • Paid Family Leave and other leaves of absence

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