Verification Engineer

Job not on LinkedIn

🔥 12 minutes ago

🇺🇸 United States – Remote

💵 $160k - $240k / year

⏰ Full Time

🟠 Senior

🔴 Lead

👷🏻‍♀️ Engineer

👻 Ghost score 2%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Delos Data

WebsiteLinkedInAll Job Openings

11 - 50 employees

🏭 Manufacturing

💼 Consulting

📦 Logistics

Manufacturing • Consulting • Logistics

Delos Data is a company of software, system, and silicon experts building specialized interconnects and infrastructure optimized for AI inference. They focus on distributing compute and memory efficiently to make inference faster and more responsive, offering real-time visibility into always-on AI infrastructure and positioning their technology for enterprise AI deployments. Delos emphasizes inference-specific networking and hardware design rather than repurposing HPC or cloud training solutions, and they engage with the AI community at events like NVIDIA GTC.

📋 Description

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies • Create and execute coverage-driven verification plans aligned with design specifications • Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases • Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers • Implement and track functional and code coverage, driving verification to closure • Develop reusable verification components and write SystemVerilog Assertions (SVA) • Participate in design and verification reviews, providing input on design testability, correctness, and optimization • Automate regression testing and enhance verification infrastructure using Python and scripting • Contribute to continuous improvement of verification processes, tools, and methodologies

🎯 Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field • 7+ years of experience in digital design verification • Strong hands-on experience with UVM-based or similar verification methodologies • Proficiency in SystemVerilog, UVM, and Python • Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) • Solid understanding of digital design fundamentals • Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB • Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C • Strong analytical and problem-solving skills • Clear written and verbal communication skills for cross-functional collaboration • High attention to detail and ability to deliver reliable, high-quality verification outcomes • Ability to work independently and manage tasks to completion • Experience with formal verification techniques and tools • Experience verifying processor subsystems or SoC-level designs • Authorization to work in the United States is addressed in the application form • Visa sponsorship requirements for work in the United States are addressed in the application form

🏖️ Benefits

• Meaningful equity • Benefits • 401(k)