Senior Staff RTL Verification Engineer

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University of Washington, Department of Electrical & Computer Engineering

WebsiteLinkedInAll Job Openings

501 - 1000 employees

Founded 1905

📚 Education

🔬 Science

Education • Engineering • Science

University of Washington, Department of Electrical & Computer Engineering is an academic department that focuses on advancing education and research in electrical and computer engineering. It provides a range of undergraduate and graduate programs, emphasizes innovation in engineering, and conducts cutting-edge research in various fields such as microelectronics, robotics, and quantum technology. The department fosters a diverse and inclusive community and offers numerous opportunities for students to engage in hands-on learning, research, and collaboration with industry leaders.

📋 Description

• Contribute to verification of next-generation RAIN RFID Reader ICs through all phases of product development • Define and develop verification methodologies and infrastructure • Develop bus functional models, subsystem behavioral models, RTL code, and SystemVerilog testbenches • Write and execute directed and constrained-random tests to achieve comprehensive functional coverage • Define verification coverage metrics for high-quality IC tape-out • Create SystemVerilog assertions, coverage monitors, and detailed test plans • Develop CI/CD workflows and custom toolkits for automation and reporting • Collaborate with logic, analog, test, and systems engineering teams to deliver features and products • Support continuous improvement of existing RAIN RFID products through feature and performance enhancements

🎯 Requirements

• Bachelor’s degree in Electrical or Computer Engineering with 12 years of experience, or 8 years with an MS, or 5 years with a PhD required • 12+ years of experience in RTL verification • Experience verifying microcontroller microarchitectures and complex finite-state machines • Experience creating and implementing RTL functional verification test plans • Experience defining and developing bus functional models, subsystem behavioral models, and architectural checkers • Expertise in SystemVerilog and Universal Verification Methodology (UVM) • Hands-on experience developing SV assertions, reusable sequences, and coverage monitors • Ability to bring complex designs from concept through tape-out and production • Familiarity with CI/CD systems and RTL coverage tools • Scripting proficiency in Perl, Python, Ruby, or UNIX shell • Excellent written and verbal communication skills • Must satisfy applicable U.S. export-control requirements; additional national-identity documentation may be required

🏖️ Benefits

• Merit increases • Annual bonus • Stock • Sales incentives for eligible roles • Healthcare benefits for US-based employees • 401(k) plan and company match • Support for remote work • Weekly Q&A sessions with the executive team • Open paid-time-off policy • Work/life balance • Reasonable accommodation for individuals with disabilities • Competitive benefits • Diverse and inclusive work environment