
11 - 50 employees
Founded 2026
đ§ Hardware
đ¤ Artificial Intelligence
đ¤ B2B
Hardware ⢠Artificial Intelligence ⢠B2B
TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functionsâXPUs, switches, connectivity, power, and system scalingâand it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.
đĽ 0 minutes ago
đşđ¸ United States â Remote
â° Full Time
đ´ Lead
đ§âđ§ Mechanical Engineer
đť Ghost score 25%
DAC
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11 - 50 employees
Founded 2026
đ§ Hardware
đ¤ Artificial Intelligence
đ¤ B2B
Hardware ⢠Artificial Intelligence ⢠B2B
TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functionsâXPUs, switches, connectivity, power, and system scalingâand it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.
⢠Own end-to-end analog block development, including requirements definition, architecture, transistor-level design, simulation, and signoff ⢠Design and optimize analog/mixed-signal circuits, including amplifiers, references, biasing, regulators, comparators, oscillators/clocking, data converters, and sensor/AFE front ends ⢠Drive performance across PVT corners, mismatch/Monte Carlo, aging/reliability considerations, and realistic loading or interaction with surrounding blocks ⢠Partner with layout on floorplanning, matching/guarding strategies, parasitic-aware design, and post-layout closure using PEX ⢠Develop and maintain testbenches, modeling collateral, and documentation for verification and integration ⢠Support silicon bring-up and debug by correlating lab data to simulations, root-causing issues, and implementing design fixes or ECOs ⢠Collaborate with digital, firmware, DFT, validation, and product engineering teams to ensure system-level success ⢠Improve design methodologies through reusable circuits, checklists, signoff flows, and scalable best practices ⢠Deliver analog blocks meeting specifications with margin across PVT, mismatch, and post-layout effects ⢠Support crisp design reviews, rapid silicon bring-up, efficient cross-functional execution, and reduced cycle time
⢠5+ years of experience in analog or mixed-signal IC design ⢠Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems ⢠Proficiency with industry-standard EDA tools and simulation flows, such as Spectre/HSPICE, ADE, and waveform/debug tooling ⢠Experience closing designs through post-layout parasitics and across process/voltage/temperature corners ⢠Ability to translate ambiguous system needs into clear block requirements and executable design plans ⢠Strong debugging skills and comfort working with lab/validation teams to correlate silicon to simulation ⢠Clear communication and high ownership in cross-site, cross-functional environments ⢠Experience with high-speed or precision analog, depending on product needs ⢠Background in power management, including LDOs, bandgaps, references, protection, start-up, and transient response ⢠ADC/DAC and power-related analog experience ⢠Familiarity with reliability/ESD considerations and design-for-manufacturability practices ⢠Experience supporting production ramp, including yield learning, characterization, and test correlation
⢠Remote-friendly work arrangement ⢠Opportunity to work with a global team ⢠Opportunity to work on consequential AI/HPC semiconductor infrastructure ⢠Ownership and autonomy in defining the roadmap ⢠Work with paying customers, committed capital, and strategic investors ⢠Opportunity to build and ship real silicon products ⢠Collaborative, low-bureaucracy work environment
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