Physical Design Engineer

Job not on LinkedIn

🔥 1 hour ago

🏄 California – Remote

🏄 California – Remote

⏰ Full Time

🟠 Senior

🔴 Lead

🧑‍🔧 Mechanical Engineer

👻 Ghost score 18%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Unconventional AI

WebsiteLinkedInAll Job Openings

11 - 50 employees

🤖 Artificial Intelligence

🔧 Hardware

⚡ Energy

Artificial Intelligence • Hardware • Energy

Unconventional AI is rethinking the foundations of a computer to optimize energy efficiency for AI. Founded by experts in AI systems, analog circuits, computing theory, and neuroscience, the company aims to bring biology-scale efficiency to artificial intelligence by redesigning computing architecture and hardware to reduce power consumption for AI workloads.

📋 Description

• Lead physical implementation of complex, high-performance blocks and top-level SoC integration from RTL to GDSII • Perform floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification • Drive aggressive Power, Performance, and Area (PPA) targets • Collaborate with architects to influence micro-architecture for physical routability and timing closure • Own final sign-off, including Static Timing Analysis (STA), IR drop analysis, Electromigration (EM), and Physical Verification (DRC/LVS/ERC) • Develop and automate physical design flows and establish best practices for synthesis, formal verification (LEC), and parasitic extraction • Collaborate across digital and analog design teams to integrate custom analog mixed-signal blocks • Evaluate potential AI-tool partners that could improve chip design efficiency

🎯 Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field • 10+ years of industry experience in digital physical design • Track record of successful tapeouts on modern process nodes; 7nm, 5nm, or newer preferred • Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs • Deep understanding of physical design challenges in advanced nodes, including multi-patterning, finFET effects, and low-voltage operation • Proficiency in power integrity analysis and noise coupling mitigation • Expert-level mastery of standard EDA tool suites, such as Synopsys Fusion Compiler, IC Compiler II, or Cadence Innovus • Strong scripting skills in Tcl, Python, or Perl • Excellent written and verbal communication skills • Experience managing deliverables from external vendors or design houses • Preferred: experience with physical design for machine-learning accelerators or large-scale systolic arrays • Preferred: experience integrating large custom analog macros and complex power-sequencing requirements • Preferred: hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques • Preferred: familiarity with state-of-the-art AI tools to accelerate chip design

🏖️ Benefits

• Best-in-class health benefits • 401k matching • Truly unlimited PTO • Complimentary meals in the Mountain View office • Massive ownership and an outsized opportunity to drive change • Comprehensive package