Design Verification Engineer

🕒 August 10

🇮🇳 India – Remote

⏰ Full Time

🟡 Mid-level

🟠 Senior

✍️ Designer

👻 Ghost score 31%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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TYLsemi

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2026

🔧 Hardware

🤖 Artificial Intelligence

🤝 B2B

Hardware • Artificial Intelligence • B2B

TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functions—XPUs, switches, connectivity, power, and system scaling—and it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.

📋 Description

• Develop and execute verification test plans for IPs, subsystems, and SoC components • Create and maintain SystemVerilog/UVM-based verification environments • Write directed and constrained-random test cases to validate design functionality • Develop functional coverage models and assist in coverage closure activities • Debug simulation failures and collaborate with design engineers to resolve issues • Write assertions (SVA) to improve design checking and verification quality • Participate in regression execution, result analysis, and reporting • Support IP integration and subsystem-level verification activities • Learn and apply industry-standard verification methodologies and best practices • Contribute to automation scripts for regression, reporting, and verification productivity • Work closely with Design, Architecture, and Software teams to understand requirements and verify functionality

🎯 Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field • 5+ years of experience in Design Verification or Digital Design • Strong understanding of digital design fundamentals and computer architecture • Knowledge of Verilog/SystemVerilog • Knowledge of UVM methodology • Knowledge of simulation and debugging concepts • Knowledge of functional and code coverage • Basic scripting in Python, Perl, Shell, or TCL • Familiarity with verification tools from Synopsys, Cadence, or Siemens EDA • Good analytical and debugging skills • Understanding of common bus protocols such as AXI, APB, AHB, PCIe, or Ethernet is a plus • Internship or academic project experience in ASIC/SoC verification is preferred • Exposure to SystemVerilog assertions (SVA) is preferred • Knowledge of constrained-random verification techniques is preferred • Experience with Python-based automation is preferred • Understanding of AI, HPC, or Networking architectures is a plus • Familiarity with Git or other version-control systems is preferred • Strong communication and teamwork abilities

🏖️ Benefits

• Remote-friendly work arrangement • Opportunity to work with a global team • Opportunity to work on cutting-edge SoCs and IPs for AI, HPC, and Networking • Opportunity to contribute to next-generation semiconductor technologies • Opportunity to work with experienced verification engineers and architects • Opportunity to work on consequential silicon infrastructure for AI • Strategic investors, committed capital, and a clear path to revenue