Lead Analog / Mixed-Signal Layout Engineer

🔥 4 hours ago

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TYLsemi

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2026

🔧 Hardware

🤖 Artificial Intelligence

🤝 B2B

Hardware • Artificial Intelligence • B2B

TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functions—XPUs, switches, connectivity, power, and system scaling—and it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.

📋 Description

• Lead layout planning, floorplanning, and execution for analog and mixed-signal blocks on FinFET-based advanced nodes • Define and enforce analog layout techniques: matching, symmetry, common-centroid structures, guard-ringing, shielding, and parasitic-aware placement/routing for sensitive analog nets • Own integration guidelines between analog/mixed-signal blocks and digital logic • Identify and resolve advanced-node layout issues — including multi-patterning (MP) constraints, color-aware routing • Drive DRC/LVS/PERC/antenna closure and coordinate ECO layout cycles with design and verification teams • Manage layout schedules, milestones, and quality across internal teams and external layout vendors/subcontractors • Interface with packaging teams for integration on advanced packaging layout requirements • Define and drive layout methodology strategy, including use of APR tools and custom scripting/automation to improve efficiency • Mentor junior layout engineers and establish reusable layout methodologies, checklists, and best-practice documentation.

🎯 Requirements

• Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related field • 10+ years of layout experience in the semiconductor industry, with significant time on FinFET process nodes (16nm and below) • 2+ years of leadership experience, such as leading a layout team, mentoring engineers, or owning layout schedules/deliverables across a project • Strong hands-on expertise in analog/mixed-signal layout techniques for power management, reference, or precision analog circuits • Deep familiarity with advanced-node layout constraints: multi-patterning, restricted design rules, device orientation/matching rules, and layout-dependent effects • Proven experience defining or applying analog-digital integration guidelines at the block and top level • Familiarity with layout automation and APR methodologies, and their applicability/limitations for analog and mixed-signal design • Track record of managing or closely collaborating with external layout teams, design service providers, or offshore layout groups • Proficiency with industry-standard layout/verification tools (e.g., Cadence Virtuoso, Calibre DRC/LVS/PERC) • Solid understanding of parasitic extraction, IR drop, EM/reliability considerations for power-carrying layout.

🏖️ Benefits

• Remote-Friendly, Global Team • No Politics, No Bureaucracy • Move Fast, Ship Real Products