ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead

🔥 0 minutes ago

🏄 California, North Carolina, +2 more states – Remote

🏄 California – Remote 🌲 North Carolina – Remote 🤠 Texas – Remote ☕ Washington – Remote

💵 $192.4k - $275.8k / year

⏰ Full Time

🟠 Senior

🔧 Hardware Engineer

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Cisco

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1984

🔧 Hardware

🔐 Security

🏢 Enterprise

Hardware • Security • Enterprise

Cisco is a multinational technology company that provides networking hardware, software, and services to enterprises, service providers, and governments. It builds routers, switches, optical transceivers, programmable silicon, and edge computing platforms, and offers security, collaboration (Webex), observability, and AI-enabled software and support services to help organizations design, operate, and secure large-scale networks and data centers. Cisco also delivers professional services, training, and cloud-managed solutions to support digital transformation and AI-ready infrastructure.

📋 Description

• Develop, document, and implement design rules for ultra-high-speed signaling • Analyze substrate signal integrity and power integrity • Collaborate with layout teams on solutions across interposer, substrate, and PCB • Design, document, and develop ASIC packages for high-volume, high-quality release • Perform post-layout extraction and reporting • Collaborate with system partners, vendors, and design leads to resolve complex technical issues • Define processes, methods, and tools for complex ASIC/package development • Lead or participate in chip architecture discussions and high-performance ASIC design • Review intricate IC and analog/mixed-signal circuit designs • Mentor the signal integrity team and junior engineers • Influence packaging and hardware teams to meet technical specifications • Promote design reviews, postmortems, and continuous improvement across engineering teams

🎯 Requirements

• Bachelor’s degree in Electrical Engineering and 10+ years of relevant signal and power integrity experience, or Master’s degree and 8+ years, or PhD and 4+ years • Expertise in Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis • Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction • Experience with pre- and post-layout SI/PI simulations • Proficiency with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS • Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows • Working knowledge of SPICE • Skilled in articulating technical concepts to diverse audiences, verbally and in writing • Experience with HBM or high-speed memory interface SI • Experience with die-to-die interfaces such as UCIe or proprietary interfaces • Experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs • Working knowledge of Vector Network Analysis • Basic knowledge of IBIS

🏖️ Benefits

• Medical, dental and vision insurance • 401(k) plan with a Cisco matching contribution • Paid parental leave • Short- and long-term disability coverage • Basic life insurance • Cisco restricted stock unit grants may be available • 10 paid holidays per full calendar year • 1 floating holiday for non-exempt employees • 1 paid day off for employee’s birthday • Paid year-end holiday shutdown • 4 paid days off for personal wellness • 16 days of paid vacation time per full calendar year for non-exempt employees • Flexible vacation time off program with no defined limit for eligible exempt employees • 80 hours of sick time off provided on hire date and each January 1st thereafter • Up to 80 hours of unused sick time carried forward • Additional paid time away for critical or emergency family issues • Optional 10 paid volunteer days per full calendar year • Annual bonuses for non-sales roles, subject to Cisco policies