Lead STA Engineer

🕒 September 15

🏄 California, Pennsylvania, +1 more states – Remote

🏄 California – Remote 🔔 Pennsylvania – Remote 🤠 Texas – Remote

💵 $180k - $260k / year

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 6%

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Efficient Computer

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🏭 Manufacturing

🔧 Hardware

🤖 Artificial Intelligence

Manufacturing • Hardware • Artificial Intelligence

Efficient Computer is a technology company developing ultra-energy-efficient processors and accompanying toolchains for edge and embedded computing. Their Fabric spatial dataflow processor architecture and E1 processor target extreme low-power applications (wearables, satellites, industrial sensors) while the effcc compiler enables developers to run familiar languages and AI/ML frameworks on the new hardware. The company focuses on delivering high-performance, long-lived battery operation and customers are primarily device makers and industrial/space operators.

📋 Description

• Drive and develop timing flows and methodology for state-of-the-art FinFET and multi-patterning-based technologies from scratch in Cadence Tempus or Synopsys PrimeTime • Own and drive timing convergence of IP, subsystem, and SoC blocks • Define timing margining, PVTRC corner definitions, extraction methodology, and signoff timing to synthesis/place-and-route correlation • Develop slew-rate and glitch-noise checks to ensure robust design quality • Develop custom timing checks for Efficient's proprietary ultra-low-power architecture • Work closely with RTL, DFT, and IP vendor teams to define and drive SDC constraints • Understand all collateral for hard and soft IP used by the design • Partner with post-silicon product bring-up teams to ensure pre-silicon to post-silicon timing correlation • Work with third-party vendor resources and coordinate timing-domain work • Continuously improve flow consistency and efficiency across multiple product-type swim lanes

🎯 Requirements

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience • Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies • Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques • Hands-on experience in timing convergence of high-frequency and low power designs • Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining • Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring optimal tradeoffs • Excellent scripting skills in TCL, shell and Python • Knowledge of computer architecture • Knowledge of physical design and ASIC implementation • Experience in full chip sign-off budgeting • Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design • Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers • Definition of design constraints for static timing analysis and corners/voltage definitions • Experience integrating analog or mixed-signal macro on top-level design

🏖️ Benefits

• 10% annual bonus • Meaningful equity • 401K match • Company-paid benefits • Paid parental leave • Flexibility • Personal and professional development opportunities

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