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Mixed Signal IC Layout Engineer

🔥 0 minutes ago

🏄 California – Remote

infoinfo

💵 $100k - $500k / year

⏰ Full Time

🟠 Senior

🔴 Lead

👷🏻‍♀️ Engineer

Where this job comes from

Posted on Tenstorrent Inc.'s careers page, not through a job board

First seen by Remote Rocketship 0 minutes ago

Logo of Tenstorrent Inc.

Tenstorrent Inc.

51 - 200 employees

Founded 2016

🏭 Manufacturing

💼 Consulting

🤖 Artificial Intelligence

Manufacturing • Consulting • Artificial Intelligence

Tenstorrent is a cutting-edge technology company based in Santa Clara, CA, specializing in AI semiconductors and computing solutions. They have developed advanced products like the TT-QuietBox, a liquid-cooled workstation designed for AI model development, and the Tenstorrent Galaxy, a high-performance AI compute server. Recently, Tenstorrent secured over $693M in Series D funding to enhance its AI chip capabilities and challenge market leaders in the AI data center sector.

📋 Description

• Execute full-custom analog/mixed-signal layout for key blocks from schematics to manufacturable layouts • Develop optimized block and top-level floorplans, placement, and routing • Balance area, parasitics, matching, congestion, and integration into the D2D PHY • Optimize resistance/capacitance parasitics, coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals • Close DRC, LVS, ERC, DFM, and Antenna requirements • Support post-layout extraction and simulation • Contribute layout methodology and automation scripts using Python, Tcl, SKILL, etc. as a bonus • Integrate high-speed analog/mixed-signal IP into complex D2D PHYs across digital, analog, and I/O domains

🎯 Requirements

• Experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks, including PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, and high-speed I/Os • Proficient with Synopsys Custom Compiler or Cadence Virtuoso • Proficient with Synopsys ICV or Siemens Calibre for DRC, LVS, ERC, DFM, and Antenna physical verification • Deep experience in CMOS/FinFET nodes, ideally TSMC or Samsung 12nm–2nm • Delivered silicon experience • Strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts • Typically hold a BSEE or equivalent experience • Approximately 10+ years in analog/mixed-signal layout • Able to own complex blocks independently and collaborate effectively with circuit designers • Eligible to access U.S. export-controlled technology; employment may depend on citizenship/permanent residency status or prior license approval

🏖️ Benefits

• Highly competitive compensation package • Benefits • Equal opportunity employer

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