Analog Engineer, Senior

🔥 1 hour ago

🇩🇪 Germany – Remote

⏰ Full Time

🟠 Senior

🔴 Lead

🧑‍💻 Full-stack Engineer

👻 Ghost score 10%

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Ciena

WebsiteLinkedInAll Job Openings

5001 - 10000 employees

Founded 1985

📡 Telecommunications

🔧 Hardware

💰 Series C on 1995-12

Telecommunications • Hardware • Networking

Ciena is a global leader in optical and routing systems, services, and automation software. We build the world’s most adaptive networks to address ever-increasing digital demands for richer, more connected experiences for all users. For three-plus decades, we’ve brought our innate sense of humanity to our relentless pursuit of innovation.

📋 Description

• Own schematic-level design and post-layout verification of high-speed transmitter signal paths and linear chains, including DAC-based output stages, high-swing/high-speed driver interfaces, ESD, and bump • Work with management, system designers, and lab validation teams to evolve architecture and meet standard and product requirements • Evaluate circuit topologies and recommend implementations based on power, area, bandwidth, and technology tradeoffs • Collaborate with layout and design engineers to deliver designs through full GDSII integration • Drive extraction-based post-layout simulations and validate transmitter performance across process, voltage, and temperature conditions • Perform root-cause analysis of design and post-layout performance gaps and implement corrective design actions • Track block- and transmitter-level performance and power against agreed targets • Translate architecture and system requirements into transmitter implementations and feed design and silicon learnings into future architecture • Build and use behavioral/design models such as MATLAB and Verilog-A • Partner with lab validation teams to correlate silicon results with simulations and support test-chip, product bring-up, and characterization • Provide technical guidance and mentorship to junior design and layout engineers • Report status and share experience with the group regularly

🎯 Requirements

• M.S./PhD in Electrical Engineering or Computer Engineering, or applicable scientific discipline • 10+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post-layout verification • Experience with transmitter circuit building blocks including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits • Experience executing post-layout and extraction-based simulations across process, voltage, and temperature conditions • Experience delivering analog circuit designs through silicon validation • Utilization of Cadence, Mentor, or Synopsys tools, including Virtuoso, Calibre, STAR-RC, and MMSIM • Demonstrated written and verbal communication skills • Ability to work independently and within a team environment • Experience with 224G or 448G PAM4 or PAM6 SerDes and related OIF-CEI or IEEE standards • Experience contributing to transmitter architecture using MATLAB, Verilog-A, or C++ • Experience with signal integrity, power integrity, channel, and package co-design methodologies, including EM tools such as HFSS or EMX • Experience mentoring engineers within analog macro design teams • Experience with mixed-signal validation using high-speed measurement and probing equipment

🏖️ Benefits

• Flexible work environment • Employee-focused culture prioritizing individual growth, well-being, and belonging • Diversity, equity, and inclusion commitment • Reasonable workplace accommodation measures for candidates with disabilities