Senior Manager, Embedded Memory

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Silvaco Inc

WebsiteLinkedInAll Job Openings

201 - 500 employees

🔧 Hardware

🤝 B2B

🔬 Science

💰 $5M Convertible Note - Silvaco on 2024-04

Hardware • B2B • Science

Silvaco Inc is a provider of semiconductor design and simulation software and silicon IP, offering TCAD and SPICE device modeling, process-to-signoff simulation flows, analog/mixed-signal circuit design and layout tools, and a portfolio of physical and interface IP (standard cell libraries, memory compilers, MIPI PHYs, embedded processors, and automotive/IoT IP). The company supports foundry and fabless customers with process design kits, library characterization, library design, and fab technology co-optimization (FTCO) services, and also supplies solutions for power devices, photonics/optoelectronics, and low-power foundation IP.

📋 Description

• Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM. • Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets. • Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects. • Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements. • Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification. • Lead silicon validation efforts including test chip development, testing and reporting. • Lead, mentor, and grow a team of memory design engineers spanning circuit design, layout, characterization, and compiler/automation. • Set individual and team goals, conduct technical reviews, and develop career paths for engineers at multiple levels. • Allocate engineering effort across roadmap projects, customer commitments, and silicon programs; manage schedules, dependencies, and risk. • Build a culture of design rigor, peer review, and continuous methodology improvement. • Serve as the senior technical lead in presales engagements — qualifying opportunities, presenting Silvaco's memory portfolio, and shaping winning technical proposals. • Translate customer SoC requirements (frequency, voltage, density, power, port configuration, special modes) into compiler specifications and PPA commitments. • Partner with sales, field application engineers, and product management on RFQs, technical evaluations, and competitive benchmarking. • Lead deep-dive technical workshops with customer architects and design teams; respond to detailed technical questionnaires and audit-style reviews. • Own PPA analysis across the memory portfolio — performance, power (active and leakage), area, and yield — at both the instance and SoC-aggregate level. • Build and maintain competitive benchmarks against foundry and third-party memory IP; identify gaps and prioritize closure. • Drive what-if and sensitivity analysis to guide architecture trade-offs (e.g., bitcell choice, mux ratio, banking, assist circuits, voltage operating range). • Translate PPA insights into clear, customer-ready collateral: datasheets, application notes, and technical white papers. • Act as the primary technical point of contact for strategic customers throughout the engagement lifecycle — from evaluation through integration, tapeout, and silicon validation. • Lead technical reviews, integration debug, and silicon correlation discussions with customer design and product engineering teams. • Drive root-cause analysis and resolution of customer-reported issues, coordinating across design, characterization, CAD, and product teams. • Represent Silvaco in foundry partner meetings and at industry conferences as needed.

🎯 Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field. • 10+ years of embedded memory design experience, with demonstrated production tapeouts of SRAM and at least two of: ROM, 1-port register file, 2-port register file, dual-port RAM. • Deep expertise in bitcell-level circuit design, memory peripherals, self-timed paths, sense amplifier design, and assist circuit techniques. • Hands-on experience across multiple process nodes, including FinFET and/or advanced sub-7nm nodes. • Strong command of SPICE simulation, statistical and Monte Carlo analysis, Vmin/yield modeling, and reliability (BTI/HCI/EM) analysis. • Working knowledge of memory compiler architecture and automation: how compilers assemble instances, generate views (.lib, LEF, GDS, Verilog, CDL), and scale across configurations. • Hands-on experience with DFT/scan tools (Tessent, FastScan), power integrity signoff (RedHawk or equivalent), and layout verification flows (DRC, LVS, parasitic extraction). • Familiarity with RTL/Verilog modelling of memory compilers, testchip definition and silicon correlation, and SDK/automation development for compiler view generation. • Proven team leadership experience — direct management or strong technical lead role over a team of 6+ memory designers. • Demonstrated success in customer-facing technical roles: presales, PPA negotiation, integration support. • Excellent written and verbal communication skills, with the ability to present complex technical material to engineers, architects, and executives. • Proficiency with scripting (Python, TCL, Perl) and Linux-based design environments. • Experience working with AI tools, such as Claude, OpenAI, Gemini • Prior experience presenting at industry venues (ISSCC, VLSI Symposium, custom integrated circuits conferences) or contributing to memory IP standards. • Direct experience interfacing with foundry partners on PDK, bitcell qualification, and reference flow alignment.

🏖️ Benefits

• full range of medical, financial and other benefits