March 19
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• Design blocks/sub-systems/FPGAs at RTL level from high-level requirements provided by the system lead • Take ownership of block/sub-systems/system level specifications and architecture, design and implementation • Generate comprehensive documentation required for design and verification • Perform FPGA top-level/sub-system level verification • Participate in design reviews involving a larger cross-functional team
• 8+ years of digital RTL design and verification experience • Competency in scripting languages Python/Tcl/shell • Excellent interpersonal and communication skills • Demonstrate a strong discipline for thorough documentation • Ability to work autonomously, setting priorities & delivering to schedule • Degree or equivalent - Electronics / Computer Science or a related discipline Nice-to-have Skills: • Previous experience of both FPGA and ASIC design flows • System-level design/architecture experience • Experience with DSP tools • Background or understanding in Physics, including quantum technologies
• Competitive salary • Equity options • Unlimited paid holiday allowance • Flexible working options • 10% matching pension • Personal development budget • Generous parental support policy • Private health/dental insurance • Life insurance • Relocation support
Apply NowMarch 19
March 19
51 - 200
🇺🇸 United States – Remote
đź’µ $100k - $120k / year
đź’° $10.5M Venture Round on 2019-11
⏰ Full Time
đźź Senior
🎨 Product Designer (UI/UX)
đź—˝ H1B Visa Sponsor
March 19
March 19
51 - 200
🇺🇸 United States – Remote
đź’° Seed Round on 2014-01
⏰ Full Time
đźź Senior
🎨 Product Designer (UI/UX)
March 19
March 19
201 - 500
🇺🇸 United States – Remote
đź’° $30M Private Equity Round on 2017-04
⏰ Full Time
đźź Senior
🎨 Product Designer (UI/UX)
đź—˝ H1B Visa Sponsor